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Hybrid cRIO Deployment - FPGA and Scan Interface


If you've not heard of scan interface mode for development on NI's CompactRIO (cRIO) platform, there is an article here that goes into the detail. Simply put, it is a method of configuring your cRIO I\O without having to develop any FPGA or DAQmx code, instead you use variables in the Real Time (RT) code. Like with DAQmx for cRIO modules, Scan Interface mode is not compatible with all C Series modules, check out this chart for details.

So, sometimes it might be that you want to go hybrid, it is all the fashion these days! We had this recently where we wanted to access some digital I\O at low acquisition rates on a cRIO, perfect for Scan Interface mode. We also had some accelerometers being acquired by the same application, so we went Hybrid!

Our Experience

Dead easy to setup and start coding with your I\O, exactly as it says on the tin, as it were. So we'd done all our coding, got the necessary digital I\O being used in our RT code along with the associated logic, on to testing, which ran as anticipated, couple of teething issue, but in source code we passed all our tests, now onto deployment...

So, with deployment, it isn't quite as simple as compiling and building your FPGA, then building and deploying your RT application and away you go. There are some things that we found and would have been ideally setup when we started working in hybrid mode (!!), to ensure a smooth process when compiling, building and deploying.

  • Make sure you start your project in Scan Interface programming mode and add all the relevant modules to the RT Scan Resources section of the project.
  • Next, add in your FPGA target setting up all modules etc.
  • When you are ready to compile and build your FPGA, switch to FPGA programming mode, deploy the chassis settings and RT Scan Resources to the cRIO. Although the modules are set up in Scan Interface mode they are compiled as part of the FPGA build and accessed via the FPGA resources.
  • Finally, when building the RT code, remember that none of the modules set up in Scan Interface mode are accessible until you open the reference to the FPGA bit file, application or VI.

As always, this is just our expereince and we are always open for discussion and learning, so give us a shout if you have something to share in relation to this. Otherwise, if you need some experts for cRIO or LabVIEW systems, get int touch!

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